Not Applicable
Not Applicable
Field of the Invention
The present invention relates generally to digital integrators and phase-locked oscillators. More particularly, the present invention pertains to digital integrators with digital lead compensators, and to phase-locked oscillators with digital integrators that include digital lead compensators.
Phase-locked oscillators are used in transmitters for producing an output frequency that is crystal referenced, for demodulating frequency-modulated signals in radio receivers, to achieve frequency-deviation compression in frequency-modulated and phase-modulated receivers, and in various devices in which both rapid change to selected frequencies and precise frequency control are critical.
The use of phase-locked oscillators, including use thereof to achieve frequency-deviation compression in radio receivers, is taught by Lautzenhiser in U.S. Pat. No. 5,091,706, issued Feb. 25, 1992; in U.S. Pat. No. 5,497,509, issued Mar. 5, 1996; and in U.S. Pat. No. 5,802,462, issued Sep. 1, 1998.
Phase-locked oscillators can be ac modulated, dc modulated, or both, as taught by Lautzenhiser in U.S. Pat. No. 5,091,706; in U.S. Pat. No. 5,097,230, issued Mar. 17, 1992; and in U.S. Pat. No. 5,311,152, issued May 10, 1994. In addition, phase-locked oscillators can be ac and/or dc modulated using principles taught in the aforesaid Lautzenhiser patents.
In phase-locked oscillators, both a forward path and a feedback path are connected to a crystal-controlled reference oscillator by a comparing device. Phase lock is achieved when a feedback frequency from a voltage-controlled oscillator equals the frequency of the reference oscillator.
Channelization of phase-locked oscillators is achieved by dividing frequencies in the feedback path by N, as shown herein, by any of the ways taught by Lautzenhiser in the aforesaid patents, by partial N manipulation, or by nearly any other method that is conceivable.
Since channelization of the feedback path is dependent only upon the time required to divide the frequency in the feedback path by a different number, if a channelization voltage is simultaneously applied to the VCO, channelization is extremely rapid.
AC modulation of the forward path, at frequencies above the loop frequency, may be achieved by applying an analog voltage, or modulating voltage, to the VCO via a modulation resistor, as taught in the aforesaid Lautzenhiser patents, or by any other suitable means.
DC modulation of the feedback path may be achieved by digital manipulation of pulses in the feedback path, as taught by Lautzenhiser in the aforesaid patents, or by any other suitable means.
In phase-locked oscillators, an error signal is produced by a difference in a feedback frequency to a reference frequency. This error signal may be integrated by analog or digital circuitry into phase-locking information for a given channelized frequency.
In phase-locked oscillators that use an analog integrator, the error signal is time integrated. This time-integrated error signal, which is a voltage, is applied to a capacitor and to a voltage-controlled oscillator (VCO) during the integration process. The error signal disappears and integration stops when phase lock is achieved, but the capacitor has been charged to a phase-locking voltage, or a channelizing voltage.
In phase-locked oscillators that use a digital integrator, the error signal is integrated by summing clock-timed UP, DOWN, and/or ZERO error signals. Digital-to-analog (D/A) conversion changes the digitally-integrated error signal into a voltage which is applied to the VCO during the integration process. The error signal disappears and integration stops when phase lock is achieved, but the digitally-accumulated error signals have become digital phase-locking information.
The present invention provides digital integrators with digital lead compensators, and phase-locked oscillators that include digital integrators with digital lead compensators. The digital integrators include special circuitry that mimics analog circuitry for lead compensating the output of the integrator, thereby providing loop stability in phase-locked oscillators, even as analog integrators use a lead resistor in series with an integrating capacitor to achieve lead compensation and loop stability.
With regard to digitally integrating, in all embodiments the method of the present invention includes: repeatedly phase detecting, producing UP and DOWN signals in response to the repeated phase detecting steps; and integrating, or algebraically-summing, digital channelizing information, or digital phase-locking information, as a function of the UP and DOWN signals. More particularly, digitally integrating includes decoding plus one, minus one, and zero correction signals from the UP and DOWN signals; and algebraically summing the minus one, plus one, and zero correction signals into the digital channelizing information, or digital phase-locking information.
With regard to lead compensating, in all embodiments, the method of the present invention includes: decoding digital lead-compensation information from the UP and DOWN signals, and using the digital lead-compensation information to offset the output frequency in a leading direction when the digital phase-locking information is driving the output frequency toward phase lock.
In first and second embodiments, lead compensating includes analog summing of a channelizing voltage and a lead-compensation voltage subsequent to digital-to-analog (D/A) converting both the digital phase-locking information and the digital lead-compensation information. In a third embodiment, lead compensating includes digitally summing the digital phase-locking information and the digital lead-compensation information prior to digital-to-analog converting.
In frequency-hopping oscillators taught herein, the method of the present invention includes producing UP and DOWN signals by phase detecting, decoding the UP and DOWN signals into increment/decrement signals, recalling previously stored phase-locking information, parallel adding a single increment/decrement pulse to the recalled phase-locking information in accordance with a sign (plus one, minus one, and/or zero) of the increment/decrement signal, and storing the corrected phase-locking information in a RAM. That is, recalling, parallel adding, and again storing provide a step of algebraically summing.
The method of the present invention further includes recalling the corrected phase-locking information, repeatedly phase detecting, repeating the parallel adding, storing, and recalling steps at a clock frequency, thereby digitally integrating phase-locking information that is progressively corrected, stored, and recalled, one increment/decrement pulse at a time, at the clock frequency.
The method of the present invention still further includes using the repeatedly recalled phase-locking information, that is being corrected one increment/decrement pulse at a time at the clock frequency, to drive the output frequency of a voltage-controlled oscillator progressively closer to phase lock substantially simultaneous with the parallel adding, storing, and recalling steps.
In addition to lead-compensated digital integrators, the present invention includes improved digital-to-analog (D/A) converters that can be characterized as: producing analog outputs that are intentionally nonlinear; producing an output voltage of each of a plurality of higher bits that is less than twice the analog output of each of a plurality of respective lower bits; producing an output voltage from each of a plurality of higher bits that is less than the sum of a maximum output of all respective lower bits; producing analog outputs with a plurality of downward steps; producing a plurality of dual addresses; and being without holes, all irrespective of component variables.
By definition, a D/A converter has a hole if an increase by one in a digital input produces an increase in a voltage output that is at least twice as high as a normal increase in the output voltage. If a D/A converter has a hole in its output voltage, one digital input may produce an analog output that is too low to satisfy a need, such as phase locking, and the next higher digital input may produce an analog output that is too high to satisfy a need, such as phase locking.
In prior-art linear D/A converters, random selection of resistors and their resistive tolerances cause holes, dual addresses, and resultant nonlinearities to occur erratically with respect to one or more bits. In contrast, in the present invention, holes are absolutely abolished in any of the bits that are designed to function according to the present invention, dual addresses with respect to a plurality of higher bits are included in at least a plurality of higher bits, and the dual addresses are designed sufficiently large that variations in resistances of the various components can never eliminate any of the dual addresses nor interject a hole in the place of any dual address.
The nonlinear D/A converters of the present invention allow lower cost resistors to be used, and allow a larger number of bits to be processed, even when low cost resistors are used.
Therefore, the present invention includes a nonlinear D/A converter that excels over prior-art D/A converters in both performance and cost when used in phase-locked oscillators, and in learning systems such as frequency-hopping oscillators.
In summary, phase-locking information is generated by integration, or algebraic summation, of increment/decrement pulses that are produced by phase detecting. More particularly, integration includes not only phase detecting, but also, repeatedly recalling, correcting, and storing at a clock frequency. The progressively-integrated phase-locking information is used to drive the output frequency of the phase-locked oscillator progressively closer to phase lock, and the recalling, correcting, driving, and storing steps are repeated at the clock frequency until phase lock occurs.
As taught herein, the phase-locked oscillators of the present invention may use the nonlinear D/A converters of the present invention; and the integrator will develop digital phase-locking information, or digital channelizing information, that compensates for (corrects for) nonlinearities in the D/A converter and in any other analog component in a learning path. If the phase-locking information is retained for reuse, the phase-locked oscillator is a learning system. However, if the phase-locking information is not retained for reuse, the phase-locked oscillator is an adaptive system.
Finally, as taught herein, the digital integrators and phase-locked oscillators of the present invention may be used in frequency-hopping oscillators. When one of the nonlinear D/A converters is used in one of the frequency-hopping oscillators, the frequency-hopping oscillator becomes a learning system in that it learns, retains, and reuses channelizing information that compensates for nonlinearities in the nonlinear D/A converter and all other analog components in a learning path.
In a first aspect of the present invention, a method for rapidly and accurately producing channelized frequencies comprises: repeatedly phase detecting; producing UP and DOWN signals in response to the repeated phase detecting steps; integrating digital channelizing information for one of the channelized frequencies as a function of the UP and DOWN signals; driving an output frequency toward phase lock in response to the digital channelizing information; and offsetting the output frequency in a leading direction during the driving step.
In a second aspect of the present invention, a method for phase locking an output frequency to a reference frequency comprises: repeatedly phase detecting; producing UP and DOWN signals as a function of the repeated phase detecting steps; integrating digital phase-locking information as a function of the UP and DOWN signals; decoding digital lead-compensation information as a function of the UP and DOWN signals; and driving the output frequency to phase lock in response to both the phase-locking information and the lead-compensation information.
In a third aspect of the present invention, a method for phase locking an output frequency to a reference frequency comprises: repeatedly phase detecting; producing UP and DOWN signals as a function of the repeated phase detecting steps; decoding plus one, minus one, and zero correction signals from the UP and DOWN signals; algebraically-summing the plus one, minus one, and zero correction signals into digital phase-locking information; decoding digital lead-compensation information from the UP and DOWN signals; and driving the output frequency in response to both the phase-locking information and the digital lead-compensation information.
In a fourth aspect of the present invention, a method for rapidly phase locking an output frequency to a selected frequency comprises: recalling previously-stored digital information for phase locking the output frequency to the selected frequency; driving the output frequency toward phase lock with the selected frequency in response to the recalled digital information; offsetting the output frequency in a leading direction during the driving step; adaptively correcting the recalled digital information, as a function of a phase difference between the output frequency and the selected frequency, subsequent to the driving step; and digitally storing the adaptively-corrected digital information.
In a fifth aspect of the present invention, a method comprises: developing digital information for driving an output frequency to approximate phase lock with a selected frequency; storing the developed digital information; recalling the stored digital information; digital-to-analog converting bits of the recalled digital information; driving the output frequency toward the phase lock in response to the converted bits of the digital information; and the digital-to-analog converting step comprises preventing holes in an output voltage produced by the digital-to-analog converting step.
In a sixth aspect of the present invention, a method for phase locking an output frequency to a reference freequency comprises: comparing a feedback frequency with the reference frequency; producing a signal, in respons to the comparing step, that indicates whether the output frequency is too high, too low, or at phase lock; digitally integrating the signal; driving the output frequency toward the phase lock in response to the digitally-integrated signal; lead compensating the output frequency during the driving step; and the driving and lead compensating steps comprise digital-to-analog converting.
In a seventh aspect of the present invention, a method for phase locking an output frequency to a reference frequency comprises: comparing a feedback frequency with the reference frequency; producing a digital plus one, a digital minus one, or a digital zero, in response to the comparing step, depending upon whether the output frequency is too high, too low, or at phase lock; accumulatively summing the digital plus one, the digital minus one, or the digital zero, at a clock frequency; and the accumulative summing step comprises recalling, parallel adding, and storing the digital plus one, the digital minus one, or the digital zero at the clock frequency.
In an eighth aspect of the present invention, a phase-locked oscillator comprises: a phase-locked loop that includes both a forward path and a feedback path; a phase comparator that interconnects the forward path and the feedback path; a voltage-controlled oscillator that is interposed into the forward path; a parallel adder that is interposed into the forward path intermediate of the phase comparator and the voltage-controlled oscillator; and a digital integrator that is connected to the phase comparator and to the voltage-controlled oscillator, and that comprises a RAM and the parallel adder.
In a ninth aspect of the present invention, a phase-locked oscillator comprises: a phase-locked loop that includes both a forward path and a feedback path; a phase comparator that interconnects the forward path and the feedback path; a voltage-controlled oscillator that is interposed into the forward path; an integrator that is connected to the phase comparator and the voltage-controlled oscillator; and the integrator comprises means for accumulatively summing a plus one, a minus one, and/or a zero at a clock frequency.
In a tenth aspect of the present invention, a phase-locked oscillator comprises: a phase-locked loop that includes both a forward path and a feedback path, and that operates at a loop frequency; a phase comparator that interconnects the forward path and the feedback path; a voltage-controlled oscillator that is interposed into the forward path; an integrator that is connected to the phase comparator and the voltage-controlled oscillator; and the integrator comprises means for accumulatively summing a plus one, a minus one, and/or a zero at a frequency that exceeds the loop frequency.